JAVA Smart CardSmartJ

(© Copyright STMicroelectronics)


Architecture of JAVA Smart Card PlatformSmartJ

SmartJ is STMicroelectronic's proprietary implementation of an open platform project initiated in November 1997 by MEDEA (Microelectronics Developments for European Applications), a European program of pre-competitive collaborative R&D. Publicly presented in 1999, this award-winning product is to be shipped to customers in the middle of 2001.

SmartJ block diagram

Technical parameters:
 
MIPS average 25 MIPS, peak 40 MIPS
CPU 32-bit RISC, speed 33MHz
Voltage 2.7 - 5.5V 
Memory 8KB to 128KB EEPROM
Power dissipation < 10mW (compatible with contact/less operation)
Clock speed on-chip clock generation up to 50MHz,
external 1-5MHz used for I/O transmit/receive clock
Performance 15µs for DES encryption/decryption,
< 500ms for 1024-bit RSA encryption/decryption
Cryptography embedded library of specialized mathematical functions for implementing cryptographic algorithms,
fast multiply - shift for high speed software cryptography
Internal details 32-bit data paths, sixteen 32-bit registers + special-purpose registers with various lengths,
two execution modes: Native & Java, native instructions are 1 - 4 bytes,
two privilege levels: User & System

The ST22 differs from the standard Java Card model in very few ways; the primary one is the presence of an on-chip clock.

It also comes with a comprehensive development environment containing SmartJ code generation tools (C, C++ and Java compilers and an assembler/linker), a SmartJ instruction set simulator, a cycle assurance simulator and C, C++, Java and assembler source level debuggers. Users can modify or add new OS functions, modify or change key upper-layer components such as the Loader or Virtual machine, download applications after initial card issuance, rapidly port the complete software onto a new component, tailor the cryptographic library to meet the user's exact needs, and still have room for specific hardware and software blocks to be plugged in.

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References