The core RISC engine has a four-stage pipeline for native execution mode (Fetch-Decode-Execute-Writeback). When in Java mode, there is an additional stage added to the pipeline that decodes the Java bytecode and translates it to be executed as the native equivalent (Fetch-Decode-Decode-Execute-Writeback)

| MIPS | 60 MIPS |
| CPU | 32-bit RISC, speed 75MHz |
| Voltage | 2.7 - 5.5 V |
| Memory | 16 MB |
| Power dissipation | < 10mW at 5.5V, < 0.1mW in idle mode |
| Size | 2mm2 (small) |
| Flexibility | Portable non application-specific design, flexible instruction set with instructions of size 1,2,3 or 4 bytes |
| Arithmetic | Single-cycle 32-bit Multiplier allows DES encryption/decryption of 64-bit block in 0.015ms with just 200 bytes of code |
| Internal details | Four/five-stage pipeline, 24-bit memory addresses, 16 GP registers, Four maskable interrupts, two memory buses for each of data and instructions |
Perhaps even more important, Advancel provides a robust set of support tools and services for customization and software development, including software simulators, assembler, debugger, linker, loader, Java and C/C++ compiler, cryptographic librares and JavaCard VM classes and methods.
