This text is bold Current Project: Comparing Approximate Computing Frameworks
Approximate methods trade in accuracy for power and performance. These methods can be significantly more efficient in the energy they consume, their speed of execution, and their area needs, which makes them attractive in application contexts that are resilient to errors.
Providing Fairness in Heterogeneous Multicores with a Predictive, Adaptive Scheduler
Shared resources contention multicore systems results in reducing both fairness and overall system performance. Contention-aware
schedulers have been proposed to provide fairness and predictable behavior through resource management. Covering deficits of prior schedulers such as significant performance overhead or inability to support heterogeneous systems raised the need for a predictive adaptive scheduler. Our scheduler outperforms state-of-the-art contention-aware scheduler by 24% and 9% improvement in fairness and performance respectively.
Simception: Fast Flexible multicore simulator
Simception can be used to design and experiment different contention-aware scheduling policies. We verify Simception with performance output of TilePro64 manycore system. It trades in simulation accuracy for faster execution time in order to reduce algorithm development overhead.
Evaluation of cache hierarchy on power and hit/miss ratio
In this work, we tried to see how much size and associativity of Last Level Cache will change power consumption and performance(by measuring hit/miss ratio), using MARSS and McPat simulators. Graduate Computer Architecture Course.
Regional Wearleveling: An Improved WearLeveling Method in SSDs
B.Sc. Thesis: Due to limited lifetime of each memory cell in an SSD, erase cycles must be spread across chip. Regional wearleveling does not save history of erasures, but dynamically change logical address of blocks and boundaries of address translation table. Thus Regional wearleveling improved life endurance with negligible performance overhead over previous work.
Process variation of Multiprocessor System-on-Chip (MPSoC)
In this project, we achieve significant speedup over conventional algorithms by proposing a heuristic static task Scheduling algorithm for MPSoC performance and energy optimization under Process Variation.
Victim Cache in SimpleScalar
Implementing a cache that stores garbage blocks for future use, written in C.
Sign Bit Reduction Multiplier
Final project of HDL course, written in VHDL. Mor info at
Regular Expression Parser on CELL/BE Processor
A Regular Expression Parser implemented in C on CELL/BE Processor in order to fully utilize CELL BE's SIMD features to improve performance.
Design and implement a minimalistic standard cell library
By using Cadence tools, we tried to re-design and implement updated version of 45nm cell library. VLSI course.